Sundance SMT338 - Manual (Page 4)

Version 1.5 Page 4 of 19 SMT338 User Manual
List of Figures
Figure 1: SMT338 Block diagram ............................................................................................. 5
Figure 2: LVD Familly sets standard ........................................................................................ 6
Figure 3: Global Clock Buffers assignments in the Virtex ........................................................ 7
Figure 4: FPGA-DSP Communication Channels ...................................................................... 9
Figure 5: Global Reset routing. Use of FPGARESET as a global reset for designs............... 12
Figure 6: FPGA reconfiguration ............................................................................................. 13
Figure 7: SMT338 Layout ........................................................................................................ 16
Figure 8: SCSI Connector Front View (Male)......................................................................... 17
List of Tables
Table 1: Virtex-Differential I/Os Combinations ...................................................................... 15
Table 2: SMT338 connector reference table............................................................................ 16
Table 3: Differential Signals –50 WAY High-density cable Pins............................................. 17
Table 4: 40 Way SDB Connector Pins ..................................................................................... 18
Table 5: JTAG Connector ........................................................................................................ 19
Scope
This document describes the architecture, the function, the use and the interface
considerations for the SMT338. This document is intended for both the users of the SMT338
and the designer who is interested in designing the FPGA provided on the Board.