Sundance SMT338 - Manual (Page 14)

Version 1.5 Page 14 of 19 SMT338 User Manual
The design makes use of a Comm-port to pass the reconfigure command to the
SMT338 FPGA and waits for a 1 on the LSB of this Comm-Port.
If another Comm-port than Comm-port 3 is used, the pins corresponding to Comm-
port 3 on the FPGA must be tied to “1” in the FPGA (As designed in the
reconfiguration example design)
The following description is referring to Figure 8.
6) The FPGA reads the command and then warns the CPLD by sending an interrupt
(FPGARESET low) that it decoded a reconfigure command. The FPGA goes into
a RESET state and leaves Comm-port 3 available for the CPLD. (in case Comm-
port3 is used by the design).
7) On receiving the FPGARESET interrupt, the CPLD goes into the WAITCMD State
and polls Comm-port 3 for a keyword. (0xBCBCBCBC or 0xBCBCBC00)
8) On receiving the keyword,
• If it is the end-of-bitstream keyword 0xBCBCBC00, the FPGA DOES NOT get
reconfigured, the CPLD leaves Comm-port 3 available for the FPGA and
enters into an IDLE state to wait for the next interrupt.
• If it is the start-of-bitstream keyword 0xBCBCBCBC, repeat step 2 to 3).
3.4. Software tools
The SMT6338 is a suite of software support for the SMT338.
It contains:
• A library of IP cores: a Comm-port Interface and a SDB interface.
• Design examples of Comm-Port and SDB applications.
• The pin allocation file for the Virtex/E: VIRTEX_TOP.ucf.
• The conversion software needed AFTER a bitstream has been generated to
format the bitstream.
Some additional software is required:
• A CAD platform to create a schematic or VHDL design.
• A simulator to simulate the hardware designs.
• Xilinx Place & Route software such as M2.1i.
• Texas Instrument C compiler or 3L parallel C compiler.