Sundance SMT6025 v.2.9 - Manual (Page 37)

Version 2.9 Page 37 of 45 SMT6025 User Manual
17.3 Read8
Read 8 bits from the address specified.
Prototype
DWORD IFHw::Read8( UINT nBar, UINT nOffset )
17.4 Write32
Write 32 bits to the address specified.
Prototype
void IFHw::Write32( UINT nBar, UINT nOffset, DWORD dword
17.5 Write16
Write 16 bits to the address specified.
Prototype
void IFHw::Write16( UINT nBar, UINT nOffset, WORD word )
17.6 Write8
Write 8 bits to the address specified.
Prototype
void IFHw::Write8( UINT nBar, UINT nOffset, BYTE byte )
18 PCI bridge chip register access
The Sundance carrier boards use a V3 bridge chip to interface to the PCI bus.
Certain resources are assigned to the carrier board when the host boots. These
resources include I/O address range, memory range and interrupt resources.
Information about these resources is kept in the PCI bridge chip registers.
The PCI bridge chip registers hold setup and control values and implement the
mailbox registers. Although direct access to the mailbox registers (offset 0XC0 –
0xCF) is possible, it is strongly recommended that you use the
SMT6025’s built-
in support (see section 14). This is a consequence of the design of the interrupt
service routine used by the
SMT6025.
A special bus cycle on the PCI bus is used to access the PCI registers of the
carrier board. This special bus cycle does not make use of the BAR mapping,
and is therefore safe to use even if the BAR addresses have not been set up.
You should not need direct access to the PCI registers for most systems. Please
make sure that you know what you are doing before accessing the PCI bridge
chip registers. Writing incorrect values to these registers will almost certainly
crash the host.
User Manual (QCF42); Version 2.9, 22/02/02; © Sundance Multiprocessor Technology Ltd. 2002