Control register, Reset state – Sensoray 417 User Manual
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Instruction Manual
8
Status register bits have the following functions:
Control Register
The control register provides a means for forcing a coprocessor soft reset. A soft reset is invoked
when any value is written to the control register port. The value of the data written to the control
port is ignored. A soft reset has the same effect on the coprocessor as a hard system reset.
Reset State
Following a soft or hard reset, the board state is initialized as follows:
•
All channel sensor types switch to the 5-Volt, 500uV/bit range.
•
All channel filter factors are reset to zero.
•
All channels are programmed to fail high on open-sensor detection.
•
All channel alarm limits are set to min/max values that disable the alarms.
•
60 Hertz Rejection Mode is active.
•
Low-speed/High-resolution Mode is active.
Table 6: Status Register bit functions
Bit
Function
CRMT
Command Register eMpTy, when set, indicates the 417 is ready to accept a
byte into its command register. Before writing a byte to the command
register, the host must test
CRMT
and verify that it is set to logic 1.
DAV
Data AVailable, when set, indicates that the 417 data register contains a new
data byte for the host. Before reading a byte from the data register, the host
must test
DAV
and verify that it is set to logic 1.
ALARM
When active (logic 1), indicates one or more programmed channel limits
were exceeded. Activated by any limit violation. Cleared by executing the
Read Alarms command.
FAULT
Indicates (1) a board reset is in progress, or (2) a board fault has been
detected. In normal operation
FAULT
is active (logic 1) for approximately
one-half second following a board reset.
FAULT
reflects the state of the
visible red LED fault indicator on the Model 417 circuit board.
IMPORTANT NOTE: The
CRMT
,
DAV
, and
ALARM
flags are not valid when
FAULT
is active. After resetting the 417 board by means of either soft or hard
reset, the host should not attempt to handshake with the 417 until
FAULT
changes to its inactive (logic 0) state.