Measurement Computing PCM-D24/CTR3 rev.3 - Manual (Page 22)

CK1 CK0 Counter Linking
0 0 3, 16 bit counters
0 1 1, 16 bit counter (counter 0), AND
1, 32 bit counter (counter 1 cascaded into counter 2)
1 0 1, 48 bit counter (counter 0 to counter 1 to counter 2)
1 1 Not defined
Counter Gates
The counter gates are tied high through a 10K resistor. In this manner the gates are
always enabled; counting is always enabled. Counters 0 and 2 may be disabled by
bringing the gates to ground at pin 27 (CTR1 Gate) and pin 30 (CTR3 Gate). Counter
1 has no external access to the gate so counter 1 is always enabled.
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