Measurement Computing AI-EXP32 - Manual (Page 14)

AI-EXP32 User's Guide Specifications
14
Digital input/output
Table 5. Digital input specifications
Number of I/O 16 channels
Configuration Each DIO bit can be independently read from (DIN) or written to (DOUT).
The DIN bits can be read at any time whether the DOUT is active or tri-stated.
Input voltage range 0 to +15 V
Input type CMOS (Schmitt trigger)
Input characteristics
47 kΩ pull-up/pull-down resistor, 28 kΩ series resistor
Maximum input voltage range 0 to +20 V maximum (power on/off, relative to DGND pins 29,30,61,62)
Pull-up/pull-down
configuration All pins pulled up to +5
V via individual 47 kΩ resistors.
 The JP1 (DIO 8- 15) shorting block default position is pull-up or "HI."
 The JP2 (DIO 16- 23) shorting block default position is pull-up or "HI."
Pull down capability is available by placing either of the JP1 and JP2 shorting blocks in
the "LO" position.
Transfer rate (software paced) 500 port reads or single-bit reads per second, typical.
Input high voltage 1.3 V minimum, 2.2 V maximum
Input low voltage 1.5 V maximum, 0.6 V minimum
Schmitt trigger hysteresis 0.4 V minimum, 1.2 V maximum
Note 1: DGND pins (pins 29, 30, 61, 62) are recommended for use with digital input and digital output pins.
The DGND and GND pins are common and are isolated from earth ground.
Table 6. Digital output specifications
Number of I/O 16 channels
Configuration Each DIO bit can be independently read from (DIN) or written to (DOUT).
The DIN bits may be read at any time whether the DOUT is active or tri-stated
Output characteristics
47 kΩ pull-up, open drain (DMOS transistor)
Pull-up configuration All pins pulled up to +5
V via individual 47 kΩ resistors.
 The JP1 (DIO 8- 15) shorting block default position is pull-up or "HI."
 The JP2 (DIO 16- 23) shorting block default position is pull-up or "HI."
Transfer rate (software paced) Digital output – 500 port writes or single-bit writes per second typical.
Output voltage range  0 to +5 V (no external pull up resistor, internal 47
kΩ pull-up resistors
connected to +5 V by default)
 0 to +15 V maximum (Note 4)
Drain to source breakdown voltage +50 V minimum
Off state leakage current (Note 5) 0.1 µA
Sink current capability  150 mA maximum (continuous) per output pin
 150 mA maximum (continuous) for all eight channels
DMOS transistor on-resistance (drain to
source) 4
Ω
Note 2: Each DMOS transistor’s source pin is internally connected to GND.
Note 3: DGND pins (pins 29, 30, 61, 62) are recommended for use with digital input and digital output pins.
The DGND and GND pins are common and are isolated from earth ground.
Note 4: The external pull-up is connected to the digital output bit through an external pull-up resistor. Adding
an external pull-
up resistor connects it in parallel with the internal 47k Ω pull-up resistor of that
particular digital input/output bit. Careful consideration should be made when considering the external
pull-up resistor value and the resultant pull-up voltage produced at the load.
Note 5: Does not include the additional leakage current contribution that may occur when using an external
pull-up resistor.