Foxconn A88GML - Manual (Page 34)

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Advanced Chipset Features
► Memory Configuration / DRAM Timing Configuration/Internal Graphics Confugura
Press to go to its submenu.
The following six items display the values configured at the settings of "DRAM Timing Mode".
► CAS Latency
This item shows the CAS latency. The CAS Latency is the number of clock cycles that elapse
from the time the request for data is sent to the actual memory location until the data is trans-
mitted from the module.
► RAS / CAS Delay
This item displays a delay time (in clock cycles) between the CAS and RAS strobe signals.
► Row Precharge Time
This item shows the number of clock cycles taken between issuing of the precharge command
and the active command. The DRAM row precharge time is in unit of clock cycle.
► Min Active RAS
Displays the number of clock cycles taken between a bank active command and issuing of the
precharge command.
► RAS / RAS Delay
This item displays a delay time (in clock cycles) between the RAS and RAS strobe signals.
► Row Cycle
This item shows the minimum timing interval between successive active commands to the
same bank. The row cycle time is in unit of clock cycle.
CMOS Setup Utility - Copyright (C) 1985-2011, American Megatrends, Inc.
Advanced Chipset Features
Northbridge Chipset Configuration Help Item
► Memory Configuration [Press Enter]
► DRAM Timing Configuration [Press Enter]
CAS Latency :9 CLK , N/A
RAS/CAS Delay :9 CLK , N/A,
Row Precharge Time :9 CLK , N/A,
Min Active RAS :24 CLK , N/A,
RAS/RAS Delay :4 CLK , N/A,
Row Cycle :33 CLK , N/A,
► Internal Graphics Configura [Press Enter]
↑↓←→:Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help
F9:Optimized Defaults
[Press Enter]