DFI CR902-B - Manual (Page 24)

www.dfi .com Chapter 3 Hardware Installation
24
Chapter 3
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
VGA_RED B89 O Analog Analog PD 150: Red for monitor. Analog output
VGA_GRN B91 O Analog Analog PD 150: Green for monitor. Analog output
VGA_BLU B92 O Analog Analog PD 150: Blue for monitor. Analog output
VGA_HSYNC B93 O CMOS 3.3V / 3.3V Horizontal sync output to VGA monitor
VGA_VSYNC B94 O CMOS 3.3V / 3.3V Vertical sync output to VGA monitor
VGA_I2C_CK B95 I/O OD CMOS 3.3V / 3.3V PU 2.2K: to 3.3V DDC clock line (I2C port dedicated to identify VGA monitor capabilities)
VGA_I2C_DAT B96 I/O OD CMOS 3.3V / 3.3V PU 2.2K: to 3.3V DDC data line.
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
I2C_CK B33 I/O OD CMOS 3.3V Suspend/3.3V
PU 2.2K: to 3.3V
Suspend
General purpose I2C port clock output
I2C_DAT B34 I/O OD CMOS 3.3V Suspend/3.3V
PU 2.2K: to 3.3V
Suspend
General purpose I2C port data I/O line
VGA Signals Descriptions
I2C BUS Signal Descriptions
Signal Pin# Pin Type Pwr Rail /Tolerance PU/PD Description
SPKR B32 O CMOS 3.3V / 3.3V
Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.
WDT B27 O CMOS 3.3V / 3.3V Output indicating that a watchdog time-out event has occurred.
KBD_RST# A86 I CMOS 3.3V / 3.3V PU 10K: to 3.3V
Input to Module from (optional) external keyboard controller that can force a reset. Pulled high on the Module. This is a legacy artifact
of the PC-AT.
KBD_A20GATE A87 I CMOS 3.3V / 3.3V PU 10K: to 3.3V
Input to Module from (optional) external keyboard controller that can be used to control the CPU A20 gate line. The A20GATE restricts
the memory access to the bottom megabyte and is a legacy artifact of the PC-AT.Pulled high on the Module.
Miscellaneous Signal Descriptions