BECKHOFF CB1061 - Manual (Page 90)

Chapter: BIOS Settings Chipset
page 90 Beckhoff New Automation Technology CB1061
4.4.1.1.1 PCI Express Root Port
Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Root Port 2 [Enabled] ▲│Control the PCI Express Root │
│ ASPM Support [Auto] █│Port. │
│ L1 Substates [L1.1 & L1.2] █│ │
│ URR [Disabled] █│ │
│ FER [Disabled] █│ │
│ NFER [Disabled] █│ │
│ CER [Disabled] █│ │
│ CTO [Disabled] █│ │
│ SEFE [Disabled] █│ │
│ SENFE [Disabled] █│ │
│ SECE [Disabled] █│ │
│ PME SCI [Enabled] █│ │
│ Hot Plug [Disabled] █│────────────────────────────────│
│ PCIe Speed [Auto] █│→←: Select Screen │
│ Detect Non-Compliance Device [Disabled] █│↑↓: Select Item │
│ Extra Bus Reserved 0 █│Enter: Select │
│ Reserved Memory 10 █│+/-: Change Opt. │
│ Prefetchable Memory 10 █│F1: General Help │
│ Reserved I/O 4 █│F2: Previous Values │
│ PCIE LTR [Enabled] █│F3: Optimized Defaults │
│ PCIE LTR Lock [Enabled] █│F4: Save & Exit │
│ Snoop Latency Override [Manual] █│ESC: Exit │
│ Snoop Latency Multiplier [1024 ns] █│ │
│ Snoop Latency Value 60 ░│ │
│ Non Snoop Latency Override [Manual] ░│ │
│ ▼│ │
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.
 PCI Express Root Port x
Options: Disabled / Enabled
 ASPM Support
Options: Disabled / L0s / L1 / L0sL1 / Auto
 L1 Substates
Options: Disabled / L1.1 / L1.2 / L1.1 & L1.2
 URR
Options: Disabled / Enabled
 FER
Options: Disabled / Enabled
 NFER
Options: Disabled / Enabled
 CER
Options: Disabled / Enabled
 CTO
Options: Disabled / Enabled
 SEFE
Options: Disabled / Enabled
 SENFE
Options: Disabled / Enabled
 SECE
Options: Disabled / Enabled