BECKHOFF CB1061 - Manual (Page 89)

Chipset Chapter: BIOS Settings
Beckhoff New Automation Technology CB1061 page 89
4.4.1.1 PCI Express Configuration
Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration │Enable or disable PCI Express │
│ │Clock Gating for each root │
│ PCI Express Clock Gating [Enabled] │port. │
│ DMI Link ASPM Control [Enabled] │ │
│ DMI Link Extended Synch Control [Disabled] │ │
│ PCIe-USB Glitch W/A [Disabled] │ │
│ Subtractive Decode [Disabled] │ │
│ │ │
│ PCI Express Root Port 1 │ │
│ PCIE Port 2 is assigned to PCIe to PCI Bridge │ │
│ PCIE Port 3 is assigned to LAN │ │
│ PCIE Port 4 is assigned to LAN2 │ │
│► PCI Express Root Port 5 │────────────────────────────────│
│► PCI Express Root Port 6 │→←: Select Screen │
│► PCI Express Root Port 7 │↑↓: Select Item │
│► PCI Express Root Port 8 │Enter: Select │
│ │+/-: Change Opt. │
│ │F1: General Help │
│ │F2: Previous Values │
│ │F3: Optimized Defaults │
│ │F4: Save & Exit │
│ │ESC: Exit │
│ │ │
│ │ │
│ │ │
│ │ │
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.
 PCI Express Clock Gating
Options: Disabled / Enabled
 DMI Link ASPM Control
Options: Disabled / Enabled
 DMI Link Extended Synch Control
Options: Disabled / Enabled
 PCIe-USB Glitch W/A
Options: Disabled / Enabled
 Subtractive Decode
Options: Disabled
 PCI Express Root Port X
Sub menu: see "PCI Express Root Port" (page 90)