ADLINK Express-IBE2 - Manual (Page 31)

Express-IBE2 Page 31
Signal Pin Description I/O PU/PD Comment
PEG_TX14-
PEG_TX15+
PEG_TX15- D99
D101
D102
PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap.
Pull low on the Carrier board to reverse lane order. I 1.05V
PEG_ENABLE# D97 Strap to enable PCI Express x16 external graphics
interface. Pull low to enable the x16 interface. I 3.3V PU 10k 3.3V Connect to switch
SDVO / PEG
SDVO mode
Signal Pin Description I/O PU/PD Comment
SDVOB_RED+
SDVOB_RED- D52
D53 Serial Digital Video B red output differential pair.
Multiplexed with PEG_TX[0]+ and PEG_TX[0]- pair. O PCIE AC coupled on Module
SDVOB_GRN+
SDVOB_GRN- D55
D56 Serial Digital Video B green output differential pair.
Multiplexed with PEG_TX[1]+ and PEG_TX[1]-. O PCIE AC coupled on Module
SDVOB_BLU+
SDVOB_BLU- D58
D59 Serial Digital Video B blue output differential pair.
Multiplexed with PEG_TX[2]+ and PEG_TX[2]-. O PCIE AC coupled on Module
SDVOB_CK+
SDVOB_CK- D61
D62 Serial Digital Video B clock output differential pair.
Multiplexed with PEG_TX[3]+ and PEG_TX[3]-. O PCIE AC coupled on Module
SDVOB_INT+
SDVOB_INT- C55
C56 Serial Digital Video B interrupt input differential pair.
Multiplexed with PEG_RX[1]+ and PEG_RX[1]-. I PCIE AC coupled on Module
SDVOC_RED+
SDVOC_RED- D65
D66 Serial Digital Video C red output differential pair.
Multiplexed with PEG_TX[4]+ and PEG_TX[4]-. O PCIE
Not supported
SDVOC_GRN+
SDVOC_GRN- D68
D69 Serial Digital Video C green output differential pair.
Multiplexed with PEG_TX[5]+ and PEG_TX[5]-. O PCIE Not supported
SDVOC_BLU+
SDVOC_BLU- D71
D72 Serial Digital Video C blue output differential pair.
Multiplexed with PEG_TX[6]+ and PEG_TX[6]-. O PCIE Not supported
SDVOC_CK+
SDVOC_CK- D74
D75 Serial Digital Video C clock output differential pair.
Multiplexed with PEG_TX[7]+ and PEG_TX[7]-. O PCIE Not supported
SDVOC_INT+
SDVOC_INT- C68
C69 Serial Digital Video C interrupt input differential pair.
Multiplexed with PEG_RX[5]+ and PEG_RX[5]-. I PCIE Not supported
SDVO_TVCLKIN+
SDVO_TVCLKIN- C52
C53 Serial Digital Video TVOUT synchronization clock input
differential pair. Multiplexed with PEG_RX[0]+ and PEG_RX[0]- I PCIE
SDVO_FLDSTALL+
SDVO_FLDSTALL- C58
C59 Serial Digital Video Field Stall input differential pair.
Multiplexed with PEG_RX[2]+ and PEG_RX[2]-. I PCIE
SDVO_I2C_CK D73 SDVO I²C clock line to set up SDVO peripherals. I/O OD 2.5V
SDVO_I2C_DAT C73 SDVO I²C data line to set up SDVO peripherals. I/O OD 2.5V