Acrosser AR-B9612 - Manual (Page 9)

2-4 AR-B9612 User’s Guide
2.4 INTERRUPT CONTROLLER
The ALI’s M6 117 also provides two cascaded 8259 Programmable
Interrupt Controllers (PIC). They accept requests from peripherals,
resolve priorities on pending interrupts in service, issue interrupt
requests to the CPU, and provide vectors which are used as
acceptance indices by the CPU to determine which interrupt
service routine to execute.
Following is the system information of interrupt levels:
IRQ8 : Real time clock
IRQ9 : Rerouting to INT 0Ah from hardware IRQ2
IRQ10 : Spare
IRQ11 : Spare
IRQ12 : Spare
IRQ13 : Reserved for math. coprocessor
IRQ14 : Spare
IRQ15 : Reserved for watchdog
In Interrupt Level
NMI
CTRL1
IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
CTRL2
Parity check
Description
Serial port 2
Serial port 1
Spare
Spare
Spare
System timer interrupt from timer 8254
Keyboard output buffer full
Figure 2-1 Interrupt Controller