Acrosser AR-B9612 - Manual (Page 25)

3-6 AR-B9612 User’s Guide
Name Description
DRQ 0-3, 5-7 [Input] DMA Request channels 0 to 3 are for 8-bit data transfers.
DMA Request channels 5 to 7 are for 16-bit data transfers.
DMA request should be held high until the corresponding
DMA has been completed. DMA request priority is in the
following sequence:(Highest) DRQ 0, 1, 2, 3, 5, 6, 7
(Lowest)
-DACK 0-3, 5-7
[Output]
The DMA Acknowledges 0 to 3, 5 to 7 are the corresponding
acknowledge signals for DRQ 0 to 3 and 5 to 7
AEN [output] The DMA Address Enable is high when the DMA controller
is driving the address bus. It is low when the CPU is driving
the address bus
-REFRESH
[Input/Output]
This signal is used to indicate a memory refresh cycle and
can be driven by the microprocessor on the I/O channel
TC [Output] Terminal Count provides a pulse when the terminal count for
any DMA channel is reached
SBHE
[Input/Output]
The System Bus High Enable indicates the high byte SD8 -
SD15 on the data bus
-MASTER [Input] The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 microseconds or system memory may be
lost due to the lack of refresh
-MEMCS16
[Input, Open collector]
The Memory Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data memory operation
-IOCS16
[Input, Open collector]
The I/O Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data I/O operation
OSC [Output] The Oscillator is a 14.31818 MHz signal
-ZWS
[Input, Open collector]
The Zero Wait State indicates to the microprocessor that the
present bus cycle can be completed without inserting
additional wait cycle
Table 3-1 I/O Channel Signal Description