Maxim Integrated MAX2769 GPS Receiver - Manual (Page 7)

Sets AGC gain to 170 (default)
Sets bit-counter length to 1024 bits (default)
Selects sign/magnitude output format (default)
Selects 1-bit AGC (default is 1 bit)
Selects analog output driver (default is CMOS logic)
Disables LO buffer (default)
Enables temperature sensor (default)
CONF3: Test: EAFF15C
This register:
Sets the PGA gain for level/LSB at 58 (default; used only when AGC is disabled and gain is set up over SPI lines)
Chooses the nominal ADC input scale (default)
Selects the nominal loading for the output driver (default)
Enables the ADC (default)
Enables the output driver (default)
Enables the filter DC-offset cancellation circuitry (default)
Enables the IF filter (default)
Enables AGC for both channels (default is I enabled only)
Enables highpass coupling between the filter and AGC (default)
Sets a 50kHz highpass pole corner frequency (default is 20kHz)
Selects no DSP interface for data streaming (default)
Sets the default data-counter length (16394 bits/frame)
Selects 2-bit streaming (default)
Enables sync pulse outputs (default)
Enables frame sync pulse outputs (default)
Disables data sync pulse outputs (default)
Disables DSP interface reset (default)
PLLCONFIG: Test: 9EC0008
This register:
Enables the VCO in normal current mode (default)
Disables external VCO bias compensation (default)
Sets clock output driver to CMOS mode (default)
Sets clock frequency to XTAL frequency
Selects buffer nominal current of 130mA for crystal (default; range is 130mA to 700mA)
Sets capacitive load programming to 3.6pF (default; nominal for C
L
> 12pF)
Selects PLL lock detect as output at LD pin (default)
Selects nominal charge-pump operation with 0.5mA current (default)
Selects 2ns charge-pump on-time selection (default)
Selects integer-N PLL (default)
Disables power save (default is power-save enable)
Selects low-current mode for prescalar E2Cs (default is high-current mode)
DIV: Test: 0C00080
This register:
Sets N = 1536 for low-side injection (default; LO = 1536 × 1.023MHz = 1571.328MHz)
Sets R = 16 (default; step size = 16.368MHz/16 = 1.023MHz)
FDIV: Test: 8000070
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