Maxim Integrated 73M1822/73M1922 Implementers Guide - Manual (Page 8)

73M1822/73M1922 Implementer’s Guide UG_1x22_052
8 Rev. 1.0
3.2 Line-Side Device (73M1912) Configuration
The Line-side device setup includes the following procedures:
1. Barrier Synchronization
2. Initial Line State Configuration
3.2.1 Barrier Synchronization
Before the Line-side device can be initialized, the barrier must be in sync and error free. The barrier is
designed to power up the line side device and come into sync automatically upon PLL lock. The Barrier
may be expected to lose sync during an error condition or during a change in PLL settings (such as a
sample rate change or during initialization). The user should check that the device indicates barrier sync
before proceeding with line side initialization.
The following registers control the Barrier Synchronization procedure.
0x03 GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT
Write X X X X X X ? X
0x05 ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENAPOL ENDET ENSYNL ENRGDT
Write X X X X X X 1 X
0x0D LOKDET SLHS Res Res CHNGFS NRST2 NRST1 NRST0
Read ? ? X X 1/0 X X X
0x0F ENFEH PWDN SLEEP Res XIB1 XIB0 Res Res
Write X X 1/0 X X X X X