Maxim Integrated Fresno (MAXREFDES11) Nexys 3 - Manual (Page 5)

Fresno (MAXREFDES11#) Nexys 3 Quick Start Guide
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3. Included Files
The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for
Xilinx ISE version 13.4. The Verilog-based HDL design instantiates the MicroBlaze core,
the support hardware required to run the MicroBlaze, and the peripherals that interface
to the Pmod ports. This is supplied as a Xilinx software development kit (SDK) project
that includes a demonstration software application to evaluate the Fresno subsystem
reference design. The lower level c-code driver routines are portable to the user’s own
software project.
Figure 3. Block Diagram of FPGA Hardware Design