Maxim Integrated Santa Fe (MAXREFDES5) ZedBoard - Manual (Page 5)

Santa Fe (MAXREFDES5#) ZedBoard Quick Start Guide
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3. Included Files
The top level of the hardware design is a Xilinx PlanAhead Project (.prr) for Xilinx
PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides
FPGA/board net connectivity and instantiates both the Zynq® Processing System as
well as the Zynq SPI peripheral that interfaces directly to the Pmod port. A Xilinx
software development kit (SDK) project is supplied and includes an example c program
to evaluate the Santa Fe subsystem reference design. The c-code driver routines are
portable to the user’s own software project.
Figure 3. Block Diagram of FPGA Hardware Design