Appendix edid version 1.x, Kt-pcie-dvi-hdmi-i users guide, Appendix – Kontron KT-PCIe-DVI-HDMI-I User Manual
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KTD-N0800-0
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KT-PCIe-DVI-HDMI-I Users Guide
Appendix EDID version 1.x.
Descriptor structure defined in the VESA
EDID code loaded in EEPROM, used for support of TMDS displays.
Byte
Description
1.
Low Byte of DClk in 10 KHz and in HEX
2.
High Byte of DClk in 10 KHz and in HEX
3.
Horizontal Active [pixel], LSByte
4.
Horizontal Blanking [pixel], LSByte
5-Bit 7-4:
Horizontal Active [pixel], 4 MSbit (All values shall be as if 1 pixel /clock)
5-Bit 3-0:
Horizontal Blanking [pixel], 4 MSBit (Blanking = Total- Active)
6.
Vertical Active [lines], LSB
7.
Vertical Blanking [lines], LSByte
8-Bit 7-4:
Vertical Active [lines], 4 MSbit
8-Bit 3-0:
Vertical Blanking [lines], 4 MSbit (Blanking = Total- Active)
9.
HSync Offset (from Horizontal Blanking) [pixel], LSByte (Front Porch)
10.
HSync Pulse Width [pixel], LSByte
11-Bit 7-4:
VSync Offset [lines], 4 LSbit (Front Porch)
11-Bit 3-0:
VSync Pulse Width [lines], 4 LSbit
12-Bit 7-6:
HSync Offset (from Horizontal Blanking) [pixel], 2 MSBit (Front Porch)
12-Bit 5-4:
HSync Pulse Width [pixel], 2 MSbit
12-Bit 3-2:
VSync Offset [lines], 2 MSbit (Front Porch)
12-Bit 1-0:
VSync Pulse Width [lines], 2 MSbit
13.
Horizontal Image Size [pixel], LSByte
14.
Vertical Image Size [lines], LSByte
15-Bit 7-4:
Horizontal Image Size [pixel], 4MSbit
15-Bit 3-0:
Vertical Image Size [lines], 4 MSbit
16:
Horizontal Border [pixel]
17:
Vertical Border [lines]
18-Bit 7:
0 = Non-interlaced, 1 = Interlaced
18-Bit 6-5:
00 = Reserved
18-Bit 4-3:
11 = Digital Separate
18-Bit 2:
Vertical Polarity (0 = Negative, 1 = Positive)
18-Bit 1:
Horizontal Polarity (0 = Negative, 1 = Positive)
18-Bit 0:
0 = Reserved
Appendix