Cirrus Logic EV2 - Manual (Page 19)

CobraNet™ EV-2
19 Rev. 2.1
Sine Wave Generator
The FPGA contains a 32-sample, 24-bit, sine table. The table is stepped through at the
sample clock rate so the resulting fundamental frequency is 48kHz / 32 samples =
1500Hz and 3000Hz at 96kHz. Limited control over frequency and gain is provided.
Listed below are the values to write to the frequency and gain registers in the FPGA.
Frequency register data bits
AD3 AD2 AD1 AD0
Frequency
48kHz sample rate
(96kHz sample rate)
0 0 0 1 1.5 kHz (3.0 kHz)
0 0 1 0 3.0 kHz (6.0 kHz)
0 0 1 1 4.5 kHz (9.0 kHz)
0 1 0 0 6.0 kHz (12.0 kHz)
0 1 0 1 7.5 kHz (15.0 kHz)
0 1 1 0 9.0 kHz (18.0 kHz)
0 1 1 1 10.5 kHz (21.0 kHz)
1 0 0 0 12.0 kHz (24.0 kHz)
Table 8: Sine Wave Frequency Register Bit Definitions
Gain register data bits
AD1 AD0
Gain
0 0 0dB
0 1 -6dB
1 0 -12dB
1 1 -18dB
Table 9: Sine Wave Gain Register Bit Definitions