Cirrus Logic AN273 - Manual (Page 2)

AN273
2
If the EP93xx device is configured for Sync boot mode as described above, the EP93xx device will force
SDCS3 to be 16 bits wide. Software can not reprogram SDCS3 to be 32 bits wide.
To avoid this situation, configure the EP93xx device to boot in the Async mode. Refer to the Appropriate
EP93xx User's Guide for details about the memory map for Sync and Async modes. Refer to the
ARM920T Core and Advanced High Speed Bus (AHB) chapters.
Another way to avoid this situation is to use an SDRAM chip select other than SDCS3, when in Sync Boot
mode.
5. Default Static Memory Wait State
When the EP93xx device is configured for internal boot mode, it first executes the on-chip boot ROM after
reset. The boot ROM sets the Static Memory Controller (SMC) registers with a wait state value that may
be suitable for faster Flash memory devices, such as the Intel Strata Flash, but this value may not be suit-
able for other slower Flash devices.
EP93xx users that plan to use slower Flash devices are advised to configure the EP93xx for external boot
mode so that the boot ROM is bypassed. The hardware default wait state value for external boot mode is
set to its maximum to accommodate slow Flash devices.
6. 2x SSP (Synchronous Serial Port) Clock – Revision E2 only
The hard-coded divide-by-2 block in the SSP (also called SPI™) clock input path was removed for Rev
E2. This change increases the upper and lower operating range by a factor of 2. The maximum SPI clock
rate of 3.6864 MHz is now increased by 2x to 7.3728MHz.
The deletion of the hard coded divide by 2 block will require those using SSP to adjust the SSPCPSR or
the SSPCR0 register divider value if the external device can not accommodate the increased SSP clock
rate automatically.
If a mixture of revisions are used, then the CHIP_ID register can be used to identify the silicon revision
and adjust the SSP registers accordingly. The CHIP_ID register, bits 31:28, identifies the silicon revision.
The silicon revision is decoded as follows:
0000 - Rev A
0001 - Rev B
0010 - Rev C
0011 - Rev D0
0100 - Rev D1
0101 - Rev E0
0110 - Rev E1
0111 - Rev E2
If SSP is not being used, or the external SPI device can automatically accommodate the 2x clock in-
crease, then no software modifications are required.