Cirrus Logic CS61584A - Manual (Page 2)

CS61584A
2 TB261PP1
or reset depends on the interface mode. In hard-
ware mode, the driver is in high impedance un-
til REFCLK is present and four clock cycles are
input to TCLK. (assuming the CON[3:0] pins
are not set to a high impedance value). In serial
or parallel host mode, the CON[3:0] bits in the
Control B register are set to a high impedance
state by power up or reset, so in addition to the
presence of REFCLK and TCLK, the user must
set CON[3:0] to a non Hi-Z value for the out-
puts to become active.
• The RPOS and RNEG (or RDATA) digital
outputs may be forced to unframed all-ones on
a per-channel basis during host mode opera-
tion. This is done on channel “n” by setting
both LLOOP1n and LLOOP2n bits in the
Control B register to “1”. This feature is inde-
pendent of the receive LOS condition.
• The Reserved bit in the Mask Register (channel
1, bit 1) is redefined to “AAO” (Automatic All
Ones). When AAO = 1, the RPOS and RNEG
(or RDATA) digital outputs are automatically
forced to an unframed all-ones data pattern
during a receive LOS condition.
• The RPOS, RNEG, and RCLK pins are forced
to Zero (squelched) during an LOS condition.
This is overridden by enabling Local Loopback
1 (digital loopback) or by setting AAO = 1.
• An excessive zeros test that complies with
ANSI T1.231 has been added for T1 operation.
The Reserved bit in the Control A register
(channel 2, bit 7) is redefined to “EXZ” in the
CS61584A. In coder mode (CODERn = 1)
setting EXZ to 1 causes the BPV output pin to
be OR’ed with excessive zero events. In AMI
mode (AMI-Rn = 1), the BPV pin goes high for
one RCLK bit period when 16 or more zeros
are received on the RTIP/RRING pins. In B8ZS
mode (AMI-Rn = 0), the BPV pin goes high for
one RCLK bit period when 8 or more zeros are
received on RTIP/RRING. For E1 operation,
when AMI-Rn = 0 (HDB3), BPV will go high
for one RCLK cycle when four or more consec-
utive zeros are received. The EXZ bits are
disabled when the device is configured in E1-
AMI mode.
PERFORMANCE IMPROVEMENTS
• The jitter attenuator is enhanced to meet ETSI
ETS 300 011 and CTR 12 jitter attenuation
specifications in E1 mode. The -3 dB knee of
the jitter attenuator has moved from 5.5 Hz to
1.25 Hz. Setting the ATTEN[1:0] pins or
Control A register bits to “11” will place the
jitter attenuator in the receive path with a -3 dB
knee at 1.25 Hz for both T1 and E1 modes.
• The serial port output timing on the SDO pin
has been improved when data is output on the
falling edge of SCLK (SPOL = 0). The first bit
output from SDO has a setup and hold time
around the falling edge of the 9
th
SCLK cycle
(instead of the 8
th
cycle) to allow the SDI and
SDO pins to be tied together for Intel micropro-
cessors with bidirectional serial ports.
• All outputs of the device may be disabled to
facilitate circuit board testing. In hardware
mode, setting both the PD1 and PD2 pins to “1”
will power down the device and tristate all
outputs. In host mode, setting both the PD1 and
PD2 bits to “1” will put all outputs into high
impedance except the data outputs on the
processor interface (SDO or AD[7:0]).
TIMING CHANGES IN PARALLEL PORT
The timing characteristics for the host mode access
have been revised in the CS61584A. Table 2 shows
a summary of the changes. Refer to the CS61584A
data sheet for the latest timing specifications.