Cirrus Logic CS61584A - Manual

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Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS61584A
Product Technical Brief
CS61584A Enhanced Dual T1/E1 LIU
The CS61584 Dual T1/E1 LIU has been modified
and improved to create the CS61584A. The
CS61584A has all of the features and performance
of the CS61584, plus many additional features. In-
corporating these improvements made it necessary
to make several changes to the pinout and function-
ality which the user must account for when upgrad-
ing to the CS61584A. When reviewing the
following information, refer to Table 1 for a de-
scription of the pinout changes and to Table 2 for
changes to the timing specifications.
FUNCTIONAL CHANGES
• The CS61584A has two Remote Loopback
pins, RLOOP1 and RLOOP2, and one Local
Loopback pin, LLOOP. The CS61584 has one
Remote Loopback (RLOOP) and two Local
Loopbacks (LLOOP1 and LLOOP2). (See
Table 1.) Local loopback can still be selected
with the CS61584A on a per channel basis only
in conjunction with TAOS for that channel.
In addition, the LLOOP pin on the CS61584A
selects local loopback 2 - the loopback all the
way through the analog interface, rather than
local loopback 1 - the data path loopback. See
the CS61584A data sheet for a full explanation.
• During Parallel Port Host mode operation
when BTS = 1, the IPOL pin is remapped to
DTACK functionality to be compliant with
the Motorola parallel interface specification.
The polarity of the INT pin is active low when
using parallel port mode with Motorola bus
timing. See Table 1.
• In Serial Port mode, the pins SAD4 and SAD5
become ZTX1 and ZTX2, respectively. These
pins must be driven low to enable the output
drivers on TTIP and TRING. These pins were
formerly no connects in this mode. The output
drivers may also be enabled using the
CON[3:0] pins or the CON[3:0] bits in the
Control B registers. See Table 1.
• The JTAG and parallel port errata issues
contained in document ER114A2 (items 1 to 3)
are corrected. These include a restriction on the
timing of ALE relative to CS, a problem with
the input of the IDCODE register, and an
address dependent data corruption problem.
• The device no longer has to be reset following
a change in the CON[3:0] pin settings.
• The Reserved bit in the Status register (channel
2, bit 1) is redefined to be “CLKLOST.” There
is a corresponding mask bit in the Mask register
(channel 2).
• The CS61584A driver output goes to high
impedance if TCLK or REFCLK is absent.
(The CS61584 driver puts out spaces if TCLK
is absent; with no REFCLK, its behavior is
undefined.) If the jitter attenuator is in the
transmit path, the driver will go into the high
impedance state after 175 to 182 TCLK clock
cycles. If the jitter attenuator is not in the
transmit path, the driver will go to high imped-
ance after 5 to 12 TCLK clock cycles. The
output starts driving again after valid transi-
tions are detected on both REFCLK and TCLK
and TCLK has been active for four cycles.
The behavior of the CS61584A after power-up
JUL’99
TB261PP1