Cirrus Logic AN270 - Manual (Page 2)

2 AN270REV1
AN270
It is interesting to look at this application from a different perspective. Modern A/D converters utilize digital decima-
tion filters which convert the highly oversampled data to the standard audio sample rates of 44.1, 48, 96 or 192 kHz.
These decimation filters perform this function in a synchronous manner where the ratio of the input to output sample
rates is fixed, generally either 512, 256 or 128. Essentially, these digital filters downsample the A/D sampled data
to a lower sample rate in a synchronous manner. A similar procedure occurs with the digital interpolation filter in the
D/A conversion process where the input sample rate is raised to a higher sample rate prior to the digital-to-analog
conversion. Consider the fact that in the proposed application the conversion processes can easily be configured
such that the A/D and D/A conversions are always operating at a higher sample rate than the interface or network.
In this configuration, the SRC is operating as either a decimation or interpolation filter but in an asynchronous man-
ner. Essentially, the integer multiple constraint imposed by standard synchronous decimation and interpolation fil-
ters no longer applies. It is this attribute that allows the conversion processes to operate in clock domains which are
independent of the network or interface.
In this application, the output of the CS8421 is configured as a slave to the interface system clock. There are several
advantages to this approach. The first is the simplicity of changing the system sample rate. Since the conversion
process is operating asynchronously from the network, a simple change of the network Left/Right or Word clock is
all that is required to change the system sample rate, since the output sample rate of the SRC is determined by the
input Word clock. There is no longer a need to reconfigure either the A/D or D/A converters for changes in the system
sample rate. The second advantage is that the fact that the output sample rate is dependent on the frequency of the
incoming word clock which ensures that the outputs of multiple CS8421 devices are synchronous and phase-
matched. The third advantage is that it allows multiple devices to be configured in a Time Division Multiplex (TDM)
multi-channel interface.
2. ADDITIONAL FEATURES
The inclusion of the CS8421 in the system also adds additional, and valuable, functionality. These unique functions
address many of the issues and design challenges associated with networked audio systems and other high-per-
formance multi-channel applications.
• Selectable Output Data Resolution - The CS8421 utilizes full 32-bit internal processing and provides the
option to output the full 32-bit data word. In addition to the full precision 32-bit data, the device has the func-
tionality to properly dither and truncate the 32-bit data to word lengths of either 24, 20 or 16-bits. The dither
between left and right channels is uncorrelated.
• Support for all Industry Standard Data Formats - The CS8421 supports all of the industry standard data
formats including Left-Justified, Right-Justified and I
2
S. Figure 2 illustrates a typical multi-channel imple-
mentation using these formats.
• Multi-Channel TDM Interface - In addition to the standard serial audio interface, multiple CS8421 devices
can be configured to implement a multi-channel Time Division Multiplex (TDM) interface. The CS8421 can
support a 4-channel TDM at 192 kHz, 8-channels at 96 kHz and 16-channels at 48 kHz sample rates. The
block diagram for a 6-channel TDM implementation is shown in Figure 3. Additional channels can easily be
added.
• Greater Digital Stopband rejection over the CS5381 - The digital filter in the CS8421 dominates the filter
response in this application. As a result, the minimum stopband rejection is 125 dB.