Cirrus Logic AN232 - Manual (Page 5)

AN232
5
A system calibration can then be performed by first running the CS5361 or CS5381 with the high pass
filter enabled (HPF = LOW) until the filter settles. At this point, disable the high pass filter (HPF = HI),
thereby freezing the stored DC offset.
4.2 AK5393
The AK5393 will automatically initiate a calibration sequence following a reset. The CAL pin (pin 9) is an
output that indicates when a calibration sequence is in progress. This calibration technique is very similar
to that described above for the CS5361 and CS5381.
The AK5393 also has a ZCAL pin (pin 6) which allows the calibration input to be obtained from either the
analog input pins or the VCOM pins. The high pass filter can be controlled via the HPFE pin (pin 19). In
the AK5393, the high pass filter is either continuously running or completely removed from the signal path.
5. Master/Slave Selection and Digital Interface Format
The CS5361, CS5381, and AK5393 are pin compatible in terms of selecting Master/Slave operation and
digitial interface format. The pins match up as noted in Table 2.
6. Speed Mode Selection
The AK5393 supports two speed modes, “normal” and “double” as determined by the DFS pin (pin 18).
This pin is compatible with the M0 pin (pin 13) of the CS5361 and CS5381, as shown in Table 2. In this
case, the M1 pin (pin 14) of the CS5361 and CS5381 must be tied low.
7. System Clocking
The CS5361 and CS5381 are fully compatible with the clocking requirements of the AK5393. However,
there is a slight difference when operating in Master mode. If DFS = LOW, the AK5393 will generate an
SCLK that is 128
×
F
s
. The CS5361 and CS5381 generate an SCLK that is 64
×
F
s
.
The CS5361 and CS5381 offer an integrated MCLK divider, which can be controlled via the MDIV pin (pin
10). This pin allows multiple external MCLK/LRCK ratios to be supported. In order to maintain complete
compatibility between the AK5393 and the CS5361/CS5381, connect the MDIV pin (pin 10) of the
CS5361/CS5381 to GND.
8. Input Buffer Topology
The analog input buffers shown in Figures 7 and 8 of the AK5393 datasheet (dated April, 2000) will also
work for the CS5361/81. In this case, the “Bias” reference should be sourced from the VQ pin of the
CS5361/81. However, these input buffers require a large input voltage level at the input to the buffer and
attenuate the signal prior to the converter. This much signal swing is not always possible in a real system,
and not necessary to achieve the full performance of the CS5361 and CS5381.
The following sections contain a description of a single-ended to differential input buffer (comparable to
Figure 7 of the AK5393 datasheet) and a fully differential input buffer (comparable to Figure 8 of the
AK5393 datasheet). These two buffer topologies are unity gain, and therefore do not rely on a large input
voltage at the buffer input.
8.1 Single-Ended to Differential Input Buffer
Figure 4 shows a single-ended to differential analog input buffer. This buffer provides the proper biasing,
isolation from the switched capacitor currents, low output impedance, and anti-alias filtering. The second
op-amp stage is set up in an inverting configuration to produce the negative node of the differential input.
In the input buffer shown below, the second stage has unity gain, and the single-ended input level will
effectively be doubled when presented differentially to the converter. For example, a 2.8 Vpp single-end-
ed input will provide a full-scale 5.6 Vpp differential input to the CS5361/CS5381.