Cirrus Logic CS4970x4 - Manual (Page 19)

CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752F1 19
5.14 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Parameter
Symbo
l Min Typical Max Unit
Address setup before PCP_CS and PCP_DS low t
mas
5 — — ns
Address hold time after PCP_CS and PCP_DS low t
mah
5 — — ns
Read
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
t
mcdr
0 — — ns
Data valid after PCP_CS and PCP_DS low with PCP_R/W high t
mdd
— — 19 ns
PCP_CS and PCP_DS low for read t
mrpw
24 — — ns
Data hold time after PCP_CS or PCP_DS high after read t
mdhr
8 — — ns
Data high-Z after PCP_CS or PCP_DS high after read t
mdis
— — 18 ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
read
1
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_ BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
t
mrd
30 — — ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write
1
t
mrdtw
30 — — ns
PCP_RW rising to PCP_IRQ falling t
mrwirqh
— — 12 ns
Write
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
t
mcdw
0 — — ns
Data setup before PCP_CS or PCP_DS high t
mdsu
8 — — ns
PCP_CS and PCP_DS low for write t
mwpw
24 — — ns
PCP_R/W setup before PCP_CS AND PCP_DS low t
mrwsu
24 — — ns
PCP_R/W hold time after PCP_CS or PCP_DS high t
mrwhld
8 — — ns
Data hold after PCP_CS or PCP_DS high t
mdhw
8 — — ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next read 1
t
mwtrd
30 — — ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write 1
t
mwd
30 — — ns
PCP_RW rising to PCP_BSY falling t
mrwbsyl
— 2*DCLKP + 20 — ns