5 freeze (bit 2), 6 master clock divide (bit 1), 5 freeze (bit 2) 4.5.6 master clock divide (bit 1) – Cirrus Logic CS4391 User Manual

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CS4391

DS335PP4

4.5.5

Freeze (Bit 2)

Function:

This function allows modifications to the registers without the changes being taking effect until Freeze
is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the
Freeze Bit, make all register changes, then Disable the Freeze bit.

4.5.6

Master Clock Divide (Bit 1)

Function:

This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in Table 9.