Cirrus Logic AN306 - Manual (Page 2)

2 AN306REV1
AN306
2. SIMPLIFIED SYSTEM DESIGN
In the design and layout of an audio mixed signal system, the conditioning and routing of the clocks are one of the
most important considerations. Because a converter’s Master Clock signal provides the sample clock that is used
as the time base for its modulator and switched analog filters, it is typically the most sensitive to jitter and clock cou-
pling. Eliminating the need for an external Master Clock signal provides for easier signal routing, reduced potential
for electromagnetic interference (EMI), and improved jitter immunity.
2.1 Eased Signal Routing
The Master Clock is typically generated in the digital section of a mixed signal system. This high-speed clock
then needs to be routed across the board to the analog or mixed signal section in order to provide the master
clock for the converters. Since the CS4350 PLL DAC does not require a Master Clock input signal, it does
not need to be routed across the system board to reach the converter. This eases the routing necessary for
the remaining clocks.
2.2 Reduced Potential for EMI
The Master Clock is typically the fastest clock used by a mixed signal audio converter. Routing any high-
speed clock takes careful consideration in order to keep EMI to a minimum. The CS4350 PLL DAC provides
an easy way to ease EMI concerns by removing the dependency on the Master Clock, thus reducing the
number of high-speed clocks necessary to implement an audio subsystem.
2.3 Improved Jitter Immunity
As system designs become increasingly complex, the system clocking sources also become increasingly
complex. In many designs, the system clock is derived from a PLL within a large SOC (System on a Chip),
and is often used as the Master Clock source for the audio converters. The clocks generated from such
SOCs often exhibit high amounts of jitter, primarily as a result of the many asynchronous operations within
the SOC coupling into the clock signal. This high amount of jitter often limits the distortion (THD+N) perfor-
mance and dynamic range of the mixed signal systems that use the SOC generated system clock.
Because the CS4350 PLL DAC generates its Master Clock internally, the jitter on an SOC or other system
clock source is of no consequence. When locking to LRCK, the CS4350’s PLL can reject any high-frequency
jitter that may be present on the slower LRCK.
3. LOCKING TO LRCK
The CS4350’s PLL locks to the incoming LRCK signal, and locking to LRCK provides some noteworthy advantages
over locking to another clock in the system. Specifically, locking to a system or video clock requires routing a high-
speed clock to the converter and does not provide the EMI and routing advantages of locking to LRCK. Locking to
LRCK also provides for improved jitter rejection due to the lower native frequency of the left-right clock; this allows
a lower high-pass corner to be achieved in the PLL’s loop filter. When locking to LRCK, no other clocks are needed
beyond those already required in the serial PCM interface (SCLK, LRCK, and SDATA).
4. NO EXTERNAL LOOP FILTER COMPONENTS
A typical PLL consists of a phase comparator, charge pump, loop filter and a VCO. The loop filter creates an analog
filter for the internal VCO control signal. Many PLLs require the loop filter components (typically two capacitors and
a resistor) to be external to the device because of internal size constraints. The CS4350 PLL uses a PLL configura-
tion that requires no external PLL loop filter components. This allows the converter’s PLL to be self-sufficient and
also reduces the implementation cost in terms of external component price and total integration area.