Cirrus Logic CS42L73 - Manual

Copyright  Cirrus Logic, Inc. 2010
(All Rights Reserved)
Advance Product Information
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Cirrus Logic reserves the right to modify this product without notice.
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MAY ‘10
DS882PB1
Ultra Low Power Mobile Audio and Telephony CODEC
Product Overview
For the full datasheet, visit
www.cirrus.com/codec-datasheets/CS42L73
 Stereo ADC
 Dual Analog or Digital MIC Support
 Dual MIC Bias Generators
 Four DACs Coupled to Five Outputs
– Ground-Centered Stereo Headphone Amp.
– Ground-Centered Stereo Line Output
– Mono Ear Speaker Amplifier
– Mono 1 W Speakerphone Amplifier
– Mono Speakerphone Line Output for Stereo
Speakerphone Expansion
 Three Serial Ports with Asynchronous Sample
Rate Converters
 Digital Audio Mixing and Routing
Ultra Low Power Consumption
 3.5 mW Quiescent Headphone Playback
Applications
 Smart Phones, UMPCs, and MIDs
System Features
 Native (no PLL required) Support for 6/12/24
MHz, 13/26 MHz, and 19.2/38.4 MHz Master
Clock Rates in Add. to Typ. Audio Clock Rates
 Integrated High-efficiency Power Management
Reduces Power Consumption
– Internal LDO Regulator to Reduce Internal
Digital Operating Voltage to VL/2
– Step-down Charge Pump Provides Low
Headphone/Line Out Supply Voltage
– Inverting Charge Pump Accommodates Low
System Voltage by Providing Negative Rail
for HP and Line Amp
 Flexible Speakerphone Amplifier Powering
– 3.00 V to 5.25 V Range
– Independent Cycling
 Power Down Management
– Individual Controls for ADCs, Dig. MIC
Interface, MIC Bias Generators, Serial Ports,
and Output Amplifiers & Associated DACs
 Programmable Thermal Overload Notification
 High-speed I²C™ Control Port (400 kHz)
(Features continued on page 2 )
CS42L73
`
Line Outputs
Pseudo Diff. Input
-
+
+VCP_FILT
-VCP_FILT
Digital Processing
L
eve
l S
h
ift
ers
CS42L73
Decimator,
HPF,
Noise
Gate,
ALC,
Volume,
Mute,
Swap/Mono
Volume, Mute, Limiter
MCLK
Stereo
Multi-bit
ΔΣ DAC
MCLK
Stereo
Multi-bit
ΔΣ DAC
LDO
VD_FILT Headphone Outputs
Pseudo Diff. Input
-
+
+VCP_FILT
-VCP_FILT
Ear Speaker Output
VA
-
+
B
Speakerphone Line
Output (Right) -
+
VP
B
VP
Speakerphone Output
(Left) -
+
VP
A
VA
VA
Digital MIC Interface Digital MIC Interface
VL
MCLK
Stereo
Multi-bit
ΔΣ ADC
-6 to +12 dB,
0.5 dB steps
-
+
MIC 2
MIC 1
Pseudo Diff. Input
Pseudo Diff. Input
Line Input (Left)
Line Input (Right)
Pseudo Diff. Input
+10 or
+20 dB
-
+
+10 or
+20 dB
-
+
MIC 1 Bias MIC 2 Bias
MIC Bias Short Detect MIC Bias
Audio Serial Port
Voice Serial Port
Auxiliary Serial Port
Audio
Serial Port
SDOUT
SDIN
ASRC
ASRC
Voice
Serial Port
SDOUT
ASRC
Auxiliary
Serial Port
SDIN
ASRC
SDOUT
ASRC
SDIN
ASRC
-VCP_FILT
Inverting
Step-Down
VCP +VCP_FILT
+VCP_FILT
-VCP_FILT
MCLK
MCLK1
MCLK2
Control Port Control Port
VP
VD_FILT
Digital Mixer Volume, Mute, Limiter
MIC2_SDET
+
Audio Serial Port
Voice Serial Port
Auxiliary Serial Port
MIC/Line Input Path