Cirrus Logic CS4297A - Manual (Page 25)

CS4297A
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4.9 Input Mux Select Register (Index 1Ah)
SL[2:0] Left Channel Source. The SL[2:0] bits select the left channel source to pass to the ADCs for
recording. See Table 6 for possible values.
SR[2:0] Right Channel Source. The SR[2:0] bits select the right channel source to pass to the ADCs for
recording. See Table 6 for possible values.
Default 0000h. This value selects the Mic input for both channels.
4.10 Record Gain Register (Index 1Ch)
Mute Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.
GL[3:0] Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog source,
applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain adjust-
ment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain.
GR[3:0] Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog
source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain
adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain.
Default 8000h. This value corresponds to 0 dB gain and Mute ‘set’.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 SL2 SL1 SL0 0 0 0 0 0 SR2 SR1 SR0
Sx[2:0] Record Source
000 Mic
001 CD Input
010 Video Input
011 Aux Input
100 Line Input
101 Stereo Mix
110 Mono Mix
111 Phone Input
Table 6. Input Mux Selection
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute 0 0 0 GL3 GL2 GL1 GL0 0 0 0 0 GR3 GR2 GR1 GR0
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CS4297A