Cirrus Logic CRD4202-1 - Manual (Page 14)

CRD4202-1
14 DS549RD1A1
R51
NO POP
C68
NO POP
C69
NO POP
R52
NO POP
R53
NO POP
Y2
NO POP
3 1
2
4
DGND DGND
+3.3VD
DGND
XT
AL
_ O
U
T
XT
AL
_ IN
ID
1#
ID
0#
1)
2)
3)
4)
For PLL operation:
OPTIONAL PLL (Phase Locked Loop)
Populate R54 = 1K
DO NOT populate: Y1, C14, C15, and R55
Apply external oscillator to XTAL_IN (pin 2)
(CRD4202-1 can use test oscillator on Y2: ECS-8FA3)
Populate R51, R52, R53, C68, and C69 according to
your input clock rate:
clock rate (MHz) R51 R52 R53 C68 C69
14.31818 2.2K NO POP 0 ohm 0.022uF 220pF
24.576 NO POP NO POP NO POP NO POP NO POP
27 2.2K 0 ohm NO POP 0.022uF 220pF
48 2.2K 0 ohm 0 ohm 0.022uF 220pF
Test Clock Only
Figure 8. Phase Locked Loop