Cirrus Logic AN334 - Manual (Page 4)

4 AN334REV1
AN334
5. MAC ADDRESS
The line 0x1ff0: 0x6000ff2b 0x00ff0000 shows the MAC address. The MAC address is stored in a section
of the flash memory called the configuration record. The value shown here is a special default value used
for the case when an un-programmed configuration record is detected.
In this case of empty FLASH, a special MAC address of 00:60:2b:ff:ff:00 is used.
The value should be viewed as consecutive words that are byte-order-reversed, with the last word (2 bytes)
being of no significance. Units with default MAC addresses should not be used in an operational network
until the configuration record is programmed with a valid MAC address.
MAC addresses must be globally unique. Blocks of Ethernet MAC addresses for production can be obtained
directly from the IEEE or from Cirrus Logic.
The configuration record, with new MAC address, can be programmed by using the Cirrus-supplied Python
manufacturing script in conjunction with the Cirrus-supplied PACNDisco and PACNFirm COM objects.
These objects are automatically installed when CobraNet Discovery is installed.
If a valid MAC address has been previously programmed, the programmed MAC address will be shown. For
example, a MAC address of 34:12:78:56:bc:9a would be indicated by the following CID output:
"0x1ff0: 0x12345678 0x9abcxxxx" – where 'xxxx' can be anything.
6. POST RESULTS
The line, "stopped at 0x33", indicates POST has passed. If "stopped at 0x1f78" is shown instead, POST has
failed and the failure code is indicated on the previous line, "x1: 0xffffffff". The value shown here (0xffffffff)
is given in the case where no POST error was detected. Possible POST error codes are as follows.
• x1: 0x00000004 - Ethernet controller test failed. Unable to access Ethernet controller. Problem with
Ethernet controller or bus interface to Ethernet controller.
• X1: 0x00000007 - Firmware incompatible problem. Firmware is incompatible with CobraNet chip used.
• X1: 0x00000008 - Internal memory test failure. Problem with on-chip CS18101 memory.
• x1: 0x00000016 - Sample clock pull range test failed. The sample clock frequency could not be ade-
quately adjusted. There is a problem with the VCXO or supporting circuitry.
• x1: 0x00000017 - Sample clock frequency test failed. The sample clock does not appear to be operating.
There is a problem with the VCXO or supporting circuitry.
7. DISABLING THE BOOT PROCESS
There are two ways to prevent the target device from booting when the FLASH memory contains valid code.
• Ground the HS1 pin (pin 17) on the CobraNet chip. This will instruct the on-chip boot loader to skip load-
ing firmware from FLASH memory.
• Invalidate the boot record in FLASH. Invalidation of the boot record will prevent all subsequent boots.
Invalidation of the boot record is accomplished by running the included 'eboot' script instead of the 'lcm2'
script. This may require running multiple times before it is successful because CID will be conflicting with
the existing firmware that is running. Reset the target device after each time 'eboot' is run.