AMD CS5535 - Manual (Page 24)

24 AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide
Initialization 32430C
4.2.8 GeodeLink™ Control Processor Initialization
The Geode CS5535 GLCP contains the diagnostic bus, the JTAG interface clock, south bridge control, and power manage-
ment.
4.3 Virtual System Architecture™ Initialization
Virtual System Architecture (VSA) is the System Management Mode (SMM) software. VSA virtualizes PCI BARs and head-
ers for GeodeLink modules as well as its normal functions described in the AMD Geode™ GeodeROM Functional Specifi-
cation (publication ID 32087).
4.3.1 Allocate Processor Frame Buffer and VSA2 Memory
The GX processor employs a Unified Memory Architecture (UMA), meaning the frame buffer is allocated from the total sys-
tem memory. The GeodeROM code programs the amount of system memory initially needed for VSA memory. VSA can
adjust the descriptors once it is loaded. When internal video is enabled, VSA allocates the frame buffer and graphics
descriptors. The amount of memory currently allowed for frame buffer use ranges from 4 to 16 MB.
To inhibit operating system DRAM detection code from reporting the frame buffer as part of system memory, a GLIU offset
descriptor is set to send transactions to the PCI bus and program Region Configuration Registers to set the region non-
cacheable. This means that DOS, Windows
®
, OS/2, and UNIX are never aware of the graphics memory portion of system
memory. This mapping prevents unwanted access to the graphics frame buffer and other critical graphics information stored
in this area. The memory is claimed in the Virtual PCI header.
4.4 PCI Bus Initialization
The GX processor does not incorporate a standard PCI bus controller. The GX processor and CS5535 devices do not have
PCI headers. VSA emulates all the PCI headers and the GeodeLink is configured to route memory and I/O for those mod-
ules. This requires VSA to be initialized before PCI scan.
For Virtual PCI headers, VSA sets GeodeLink descriptors and the Region Control Registers as requested by the modules
during PCI scans.
PCI scan supports interrupt mapping and PCI Bridge support. There is no plan for ISA PnP support at this time.
The PCI controller configuration registers are accessed through PCI type one configuration access mechanism (using Ports
CF8h and CFCh).