AMD CS5535 - Manual (Page 21)

AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide 21
Initialization 32430C
4.2.4.1 IRQ Mapper
The XPIC has several incoming sources. They are IRQ, LPC, Y, and Z sources. The Y sources include software, USB, RTC
alarm, audio, power management, NAND Flash, SMB, KEL, and UARTs. The Z sources include eight MFGPTs and eight
GPIOs. During PCI scan, GeodeROM allocates memory, I/O, and interrupts to the PCI devices. This includes the virtual
devices emulated by VSA. VSA is responsible for the setup of the XPIC mapper for the devices it is virtualizing.
4.2.4.2 Keyboard Emulation Logic (KEL) 1+ 2
4.2.4.3 System Management Bus (SMBus)
4.2.4.4 GPIO and ICF
4.2.4.5 Multi Function General Purpose Timers (MFGPTs)
Location: I/O 20-21 master Programmable Interrupt Controller (PIC), I/O A0-A1 slave PIC, I/O 4D0 edge/level
PIC shadow register at MSR Address 51400034h
The use of the IRQ Mapper LBAR is optional since it is always accessible via MSRs. The LBAR is for
the Mask and Mapper (MM) and the extended PIC (XPIC).
Description: The IRQ Mapper is a combination of a Mapper and Mask (MM), an XPIC, and two Legacy 8259 compat-
ible PICs (LPIC).
Initialization: At reset, the PIC subsystem comes up in legacy mode. VSA initializes the XPIC to generate ASMI from
GPIOs. Devices on the XPIC are hard wired to Interrupt Groups (IG) in the MM and XPIC. The XPIC is
hooked to the LPIC on interrupts [0:1], [3:15]. The rest (16:64) are hooked to ASMI.
Location: NA
Description: Used for A20 support as well as USB keyboard emulation.
Initialization: VSA technology.
Location: 6000h
Description: SMBus is an industry standard two-wire serial interface. The SMBus is essentially an ACCESS.bus and
is the interface used to read the DRAM SPD.
Initialization: GeodeROM sets the LBAR with the desired location and the GPIOs for SMBus. The recommended
address (SMBADDR) is 0EFh.
Location: 6100h
Description: There are 23 GPIOs in Working mode and 5 in Standby mode. The GPIO registers are such that there is
no need to do read/modify/writes. GPIO registers associated with bit settings are 32 bits. Thus, 16 GPIO
may be changed at once. These are organized into Low and High banks. The Low bank deals with
GPIOs 0 through 15 while the High bank deals with GPIOs 16 through 31.
Be aware of specification update issue #113 in certain silicon revisions (as of this writing, see AMD
Geode™ CS5535 Companion Device Specification Update Silicon Revision A3 (publication ID 31534)).
After a suspend, writing the register can not be done atomically.
Initialization: VSA technology will set and use GPIOs connected with SMIs.
Many GPIOs are muxed with other signals and must be set up appropriately. There is a GPIO INT and
Power Management Event (PME) Mapper that maps GPIOs to the PIC and power management sub-
system.
Location: 6200h
Description: Timers are used by VSA mostly. The timers can set and be set by GPIOs. The timers can output to non-
maskable interrupts and cause an ASMI through the XPIC with interrupts.
Initialization: VSA technology.