Apple iMac - Manual (Page 24)

C H A P T E R 2
Architecture
24 Main Logic Board
processor’s clock speed, rather than at the clock speed of the main system bus.
In the iMac, the clock speed of the backside cache is half that of the
microprocessor.
The data storage for the backside L2 cache consists of 512 KB of fast static RAM
on the processor module.
Memory Controller and PCI Bridge 2
The memory controller and PCI bus bridge IC is a Motorola MPC106, also
called Grackle. The Grackle IC provides the bus bridge between the processor
bus used on the processor module and the PCI bus used for the ICs on the main
logic board. The Grackle IC also contains the memory controller for the main
memory.
The main memory bus runs at a clock speed of 66.67 MHz. The internal PCI bus
runs at 33.33 MHz. To enhance performance, the Grackle IC supports
concurrent transactions on the main memory bus and the PCI bus.
Information about the Grackle IC is available on the World Wide Web at
http://www.mot.com/SPS/PowerPC/products/semiconductor/
support_chips/106.html
Main Logic Board 2
All the I/O interfaces and the video display system are on the main logic board.
The controller ICs on the main logic board are connected to the PCI bus, which
also communicates with the processor module.
I/O Controller IC 2
The I/O controller IC in the Macintosh iMac computer is an ASIC called
Paddington. The Paddington IC is an integrated I/O controller and DMA
engine for use in Power Macintosh computers with a PCI bus.
The Paddington IC contains the PCI bus arbiter. It also provides the interface
and control signals for
■ the video display subsystem