Apple iMac - Manual (Page 23)

C H A P T E R 2
Architecture
Processor module 23
Processor module 2
The processor module contains the high-speed components:
■ G3 microprocessor
■ 512 KB backside cache memory
■ main memory (minimum of 32 MB)
■ system ROM (1 MB)
■ memory controller and the PCI bus bridge IC
The devices on the processor module communicate with the main logic board
by way of the PCI bus.
This section includes a description of the microprocessor, the backside cache,
and the memory controller IC. For a description of the SO-DIMMs that contain
the main memory, please see Chapter 4, “Expansion.”
G3 Microprocessor 2
The latest family of PowerPC microprocessor designs is called “G3,” for
“generation three.” The G3 microprocessors have several features that
contribute to improved performance, including:
■ larger on-chip (L1) caches, 32 KB each for instruction cache and data cache
■ a built-in cache controller and cache tag RAM for the second level (L2) cache
■ a separate backside bus for the L2 cache, providing faster clock speed and
overlapped bus transactions
■ a microprocessor core optimized for Mac OS applications
The G3 microprocessor in the iMac runs at a clock speed of 233 MHz.
Backside Cache 2
The controller and tag storage for the backside cache are built into the
microprocessor chip. The cache controller includes bus management and
control hardware that allows the cache to run at a sub-multiple of the