Teledyne LeCroy QPHY-DDR3 - Manual (Page 13)

QPHY-DDR3 Software Option
917717 Rev C
13
BASIC FUNCTIONALITY
The functionality is extracted from JEDEC Standard No. JESD79-3D, section 3.
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-
bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The
8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four
clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data
transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a “chopped” burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write command.
The address bits registered coincident with the Active command are used to select the bank and row to
be activated
(BA0-BA2 select the bank; A0-A15 select the row; refer to “DDR3 SDRAM Addressing” on page 15 for
specific requirements). The address bits registered coincident with the Read or Write command are used
to select the starting column location for the burst operation, determine if the auto precharge command is
to be issued (via A10), and select BC4 or BL8 mode on the fly (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner.