SP / Silicon Power SP008GBLTU160N02 - Manual (Page 5)

DDR3 UDIMM w/o ECC
Product Specification
Rev. 1.5 May. 2012 5
Pin Description
Symbol Type Description
A0–A14 Input
Address inputs: Provide the row address for ACTIVE commands and the column address
and auto precharge bit for READ/WRITE commands to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is sampled
during READ and WRITE commands to determine if burst chop (on-the-fly) will be
performed. The address inputs also provide the opcode during mode register command set.
A0–A13 (128Mx8) A0–A14 (256Mx8).
BA0–BA2 Input
Bank address inputs: BA0, BA1 define to which device bank an ACTIVE, READ, WRITE,
orPRECHARGE command is being applied. BA0, BA1 define which mode register,
including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
CK0, CK0#,
CK1, CK1#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE0, CKE1 Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR3 SDRAM.
DM0–DM7 Input
Data input mask: DM is an input mask signal for write data. Input data is masked when DM
issampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading is designed to match that
of DQ and DQS7pins.
ODT0
ODT1
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#
and DM. The ODT input will be ignored if disabled via the LOAD MODE command.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 ×V
DD
and DC
LOW ≤ 0.2 ×V
DD
.
S0#, S1# Input
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
SA[2:0] Input
Presence-detect address inputs: These pins are used to configure the SPD EEPROM
address range.
SCL Input
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
DQ0–DQ63 I/O Data input/output: Bidirectional data bus.
DQS0–DQS7
DQS0#–DQS7#
I/O
Data strobe: Output with read data, input with write data for source synchronous operation.
Edge-aligned with read data, center-aligned with write data.
SDA I/O
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
data into and out of the SPD EEPROM on the module.
V
DD
Supply
Power supply: 1.5V ±0.075V. The component V
DD
and V
DDQ
are connected to the module
V
DD
.
V
DDSPD
Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V.
V
REFCA
Supply Reference voltage: Control, command, and address (V
DD
/2).
V
REFDQ
Supply Reference voltage: DQ, DM (V
DD
/2).
V
SS
Supply Ground.
V
TT
Supply Termination voltage: Used for control, command, and address (V
DD
/2).
NC – No connect: These pins are not connected on the module.
NU – Not used: These pins are not used in specific module configuration/operations.