SP / Silicon Power SP001GBRDE333O01 - Manual (Page 4)

SP001GBRDE333O01
184pin DDR 333 Registered DIMM
This document is a general product description and is subject to change without notice
6. Pin Description
SYMBOL TYPE DESCRIPTION
CK, /CK Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK . Output data
(DQs and DQS /DQS) is referenced to the crossings of CK and /CK .
/RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /S) define the command being entered.
CKE Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and
Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for
self refresh exit. CKE must be maintained high throughout read and write accesses. Input
buffers, excluding CK, /CK, and CKE are disabled during power-down. Input buffers, excluding
CKE, are disabled during self refresh.
/S0-/S1 Input
Chip Select: Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
DM0-DM8 Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command.
BA0 - BA2 Input
Bank Address Inputs: BA0 and BA1 for 256 and 512Mb, BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also determines if
the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
A0 - A12 Input
Address Inputs: Provided the row address for Active commands and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the
Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code
during Mode Register Set commands.
DQ0-DQ63 Input/Output Data bit Input/ Output: Bi-directional data bus.
CB0-CB7 Input/Output ECC check bits.
DQS0-DQS8 Input/Output
Data Strobe: output with read data, input with write data for source-synchronous operation.
Edge-aligned with read data, center-aligned with write data. For Rawcards using x16 orginized
DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of
the DRAM.
NC No Connect: No internal electrical connection is present.
V DDQ Supply
Power supplies for the DDR SDRAM output buffers to provide improved noise immunity. For all
current DDR unbuffered DIMM designs,
V DDQ shares the same power plane as V DD pins
V DD , V SS Supply
Power and ground for the DDR SDRAM input buffers, and core logic. V DD and V DDQ pins are tied
to V DD / V DDQ planes on these modules.
V REF Supply Reference voltage for SSTL_2 inputs.
SDA Input/Output
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to
V DD to act as a pullup on the system board.
SCL Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to
V DD to act as a pullup on the system board.
V DD SPD Supply
Power supply for SPD EEPROM. This supply is separate from the V DD / V DDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
SA0-SA2 Input
These signals and tied at the system planar to either VSS or VDD to configure the serial SPD
EERPOM address range.
/RESET Input
The /RESET pin is connected to the /RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be
set to low level (The PLL will remain synchronized with the input clock.