SilverStone ST55GF Manual - Manual (Page 8)

Figure 2: Turn On/Off Timing
3.6 Power Good Signal: PWOK
P SOK is a power OK signal and will be pulled HIGH by the power supply to indicate that
all the outputs are within the regulation limits of the power supply. When any output voltage
falls below regulation limits or when AC power has been removed for a time sufficiently
long so that power supply operation is no longer guaranteed, PWOK will be de-asserted to a
LOW state. See for a representation of the timing characteristics of PWOK. The start of
PWOK delay time shall inhibited as long as any power supply output is in current limit.
Table 12 - PWOK Signal Characteristics
Signal
Open collector/drain output from power supply.
Pull-up to VSB located in power supply.
PWOK = High Power OK
PWOK = Low Power is Not OK
MIN MAX
Logic level low voltage, Isink = 4mA
Logic level high voltage, Isource = 200
•
A
0V
2.0V
Sink current, PWOK = Low
Source current, PWOK = High
0.4V
5.25V
4mA
2mA
PWOK delay: Tpwok_on
PWOK rise and fall time
PWOK down delay : Tpwok_off
100mSec
2mSec
1000mSec
100mSec
200mSec
AC Input
Vout
PWOK
+SVSB
PSON#
AC off AC on
Tsb_on-delay
Tac_on-delay
Tsb_vout
AC turn on/off cycle
Tpwok_on
Tsb_holdup
Tvout_holdup
Min 70mS
Tpwok_off
Tpwok_holdup
Tpwok_low
Tsb_on-delay
PSON turn on/off cycle
Tpson_on_delay
Tpwok on
Tpwok_off
Tpson_pwok
07