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Asus M2N-X User Manual

Page 15

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ASUS M2N-X

1-3

NVIDIA

®

nForce™ 520 MCP chipsets

The NVIDIA

®

nForce™ 520 media and communications processor (MCP)

builds on the award-winning single-chip, scalable architecture of the NVIDIA

nForce MCP.

DDR2 memory support

The motherboard supports DDR2 memory which features data transfer

rates of 800MHz/667 MHz/533 MHz to meet the higher bandwidth

requirements of the latest 3D graphics, multimedia, and Internet

applications. The dual-channel DDR2 architecture doubles the bandwidth

of your system memory to boost system performance, eliminating

bottlenecks with peak bandwidths of up to 12.8 GB/s. See pages 1-12 to

1-14 for details.

PCI Express™ interface

The motherboard fully supports PCI Express, the latest I/O interconnect

technology that speeds up the PCI bus. PCI Express features point-to-point

serial interconnections between devices and allows higher clockspeeds by

carrying data in packets. This high speed interface is software compatible

with existing PCI specifications. See page 1-18 for details.

AMD Cool ‘n’ Quiet Technology

The motherboard supports the AMD Cool ‘n’ Quiet Technology, which

monitors system operation and automatically adjusts CPU voltage and

frequency for a cool and quiet operating environment.

Serial ATA 3Gb/s technology

The motherboard supports next-generation SATA hard drives based on

the new SATA 3Gb/s storage specification. The onboard NVIDIA

®

nForce

520 MCP southbridge allows RAID 0, RAID 1, RAID 0+1, RAID 5, and JBOD

configurations for four SATA connectors.

10/100 Mbps LAN

Easy connectivity to your network or broadband connection with the

onboard LAN port. Allows you to play online games without buying

expensive additional LAN cards. See page 1-21 for details.

USB 2.0 technology

The motherboard implements the Universal Serial Bus (USB) 2.0

specification, dramatically increasing the connection speed from the

12 Mbps bandwidth on USB 1.1 to a fast 480 Mbps on USB 2.0. USB 2.0 is

backward compatible with USB 1.1. See page 1-26 for details.