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3 chipset chipset chipset chipset chipset, Hyper-threading technology [enabled, Advanced chipset settings – Asus P5P800 User Manual

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C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

C h a p t e r 4 : B I O S s e t u p

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Hyper-Threading Technology [Enabled]

Allows you to enable or disable the processor Hyper-Threading Technology.
Configuration options: [Disabled] [Enabled]

4.4.3

4.4.3

4.4.3

4.4.3

4.4.3

Chipset

Chipset

Chipset

Chipset

Chipset

The Chipset menu allows you to change the advanced chipset settings.
Select an item then press to display the sub-menu.

Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit

Advanced Chipset Settings

WARNING: Setting wrong values in the sections below

may cause the system to malfunction.

Configure DRAM Timing by SPD

[Enabled]

Memory Acceleration Mode

[Auto]

DRAM Idle Timer

[Auto]

DRAM Refresh Rate

[Auto]

Graphic Adapter Priority

[AGP/PCI]

Graphics Aperture Size

[ 64MB]

Spread Spectrum

[Enabled]

MPS Revision

[1.1]

Advanced Chipset Settings

Advanced Chipset Settings

Advanced Chipset Settings

Advanced Chipset Settings

Advanced Chipset Settings

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

Configure DRAM Timing by SPD [Enabled]

When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled.
Configuration options: [Disabled] [Enabled]

DRAM CAS# Latency [2.5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [2.0 Clocks] [2.5 Clocks] [3.0 Clocks]

DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [4 Clocks] [3 Clocks] [2 Clocks]

DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command.
Configuration options: [4 Clocks] [3 Clocks] [2 Clocks]