5 chipset, North bridge chipset configuration, Execute disable bit [enabled – Asus P5B Deluxe/WiFi-AP User Manual
Page 92: Hyper threading technology [enabled, Inter(r) speedstep (tm) tech. [disabled, Configuration options: [disabled] [automatic
![5 chipset, North bridge chipset configuration, Execute disable bit [enabled | Hyper threading technology [enabled, Inter(r) speedstep (tm) tech. [disabled, Configuration options: [disabled] [automatic | Asus P5B Deluxe/WiFi-AP User Manual | Page 92 / 164](/screens/308917/92.png)
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