Rainbow Electronics MAX5173 - Manual (Page 11)

MAX5171/MAX5173
Low-Power, Serial, 14-Bit DACs
with Force/Sense Voltage Output
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The MAX5171/MAX5173 accepts one 16-bit packet or
two 8-bit packets sent while CS remains low. The
MAX5171/MAX5173 allow the following to be config-
ured:
• Clock edge on which serial data output (DOUT) is
clocked.
• State of the user-programmable logic output.
• Configuration of the reset state.
Specific commands for setting these are shown in
Table 1.
The general timing diagram in Figure 4 illustrates how
the MAX5171/MAX5173 acquire data. CS must go low
at least t
CSS before the rising edge of the serial clock
(SCLK). With CS low, data is clocked into the register on
the rising edge of SCLK. The maximum serial clock fre-
quency guaranteed for proper operation is 10MHz for
the MAX5171 and 6MHz for the MAX5173. See Figure 5
for a detailed timing diagram of the serial interface.
Serial Data Output (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output; it allows for daisy-chaining of multiple
devices as well as data readback (see
Applications
Information ). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
User-Programmable Logic Output (UPO)
The UPO allows control of an external device through
the serial interface, thereby reducing the number of
Load input register; DAC registers are updated (start up DAC with new data). 1 0
Load input register; DAC registers are unchanged. 0 0
14-bit DAC data
14-bit DAC data
16-BIT SERIAL WORD
D13..................D0 C1
FUNCTION
C0
No operation (NOP). 1 1 0 0 x xxx xxxx xxxx
x x x xxx xxxx xxxx
Update DAC register from input register (start up DAC with data previously
stored in the input registers).
0 1
UPO goes low (default). 1 1 1 0 0 xxx xxxx xxxx
0 1 x xxx xxxx xxxx
Mode 1, DOUT clocked out on SCLK’s rising edge. 1 1 1 1 0 xxx xxxx xxxx
1 0 1 xxx xxxx xxxx UPO goes high. 1 1
Shut down DAC (provided PDL = 1). 1 1
Mode 0, DOUT clocked out on SCLK’s falling edge (default). 1 1 1 1 1 xxx xxxx xxxx
SCLK
DIN
CS
MOSI
SCK
+5V
I/O
CPOL = 0, CPHA = 0
SPI/QSPI
PORT
SS
MAX5171
MAX5173
Figure 2. Connections for SPI/QSPI
SCLK
DIN
CS
SK
SO
I/O
MICROWIRE
PORT MAX5171
MAX5173
Figure 3. Connections for MICROWIRE
Table 1. Serial-Interface Programming Commands