Table 2. detailed sspstat register content – Rainbow Electronics MAX1089 User Manual

Page 12

MAX1086–MAX1089

the first eight data bits starting with the MSB. The sec-
ond 8-bit data stream contains the remaining bits, D1
through D0, and the two sub-bits S1 and S0.

Layout, Grounding, and Bypassing

For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog

and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.

High-frequency noise in the power supply (V

) may

degrade the performance of the ADC’s fast comparator.
Bypass V

to the star ground with a 0.1µF capacitor,

located as close as possible to the MAX1086–MAX1089s
power supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5

Ω) if

the power supply is extremely noisy.

150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23

______________________________________________________________________________________

CNVST

SCLK

DOUT

SCK

MISO

QSPI

MAX1086–
MAX1089

Figure 9a. QSPI Connections

Table 2. Detailed SSPSTAT Register Content

X = Don’t care

D/A

CONTROL BIT

MAX1086–MAX1089

SETTINGS

SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)

Bit 5

Data Address Bit

Bit 4

Stop Bit

Bit 3

R/W

SMP

Bit 7

SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.

CKE

Bit 6

SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.

Bit 2

Bit 1

Bit 0

Start Bit

Buffer Full Status Bit

Update Address

Read/Write Bit Information

Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)

CNVST

1ST BYTE READ

SCLK

DOUT

2ND BYTE READ

SAMPLING INSTANT

MSB

LSB

HIGH-Z