Rainbow Electronics DS1678 - Manual (Page 26)

DS1678
26 of 26
NOTES:
1. After this period, the first clock pulse is generated.
2. A device must initially provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL. The maximum t
hd:dat
has only to be met if the device does
not stretch the LOW period (t
low
) of the SCL signal.
3. A fast mode device can be used in a standard mode system, but the requirement t
su:dat
> 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
r MAX
+ t
su:dat
= 1000 + 250 = 1250ns before the SCL line is released.
4. C
B
– Total capacitance of one bus line in pF.
5. t
R
and t
F
are measured with a 1.7kΩ pull-up resistor, 200pF pull-up capacitor, 1.7kΩ pull-down
resistor and 5pF pull-down capacitor.
6. V
pf
measures at V
BAT
= 3.0V.