Rainbow Electronics DS1678 - Manual (Page 16)

DS1678
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MIP - Mission in Progress – This bit indicates the sampling status of the DS1678. If MIP is logic 1, the
device is currently on a “mission” in which it is operating in the event logging mode. The MIP bit is
changed to logic 1 immediately following the activation of the
INT pin if the ME bit of the control
register contains a 1. In order to immediately start an event logging mission via the 2-wire bus, a 1 can be
written into the MIP bit and a 1 will automatically be written into the ME bit of the control register.
If MIP is logic 0, the DS1678 is not currently in event logging mode. The MIP bit transitions from logic 1
to logic 0 whenever event logging is stopped. Event logging is stopped when the DS1678 is cleared by
writing to the clear enable and memory clear bits or when any memory location including the RTC or
control registers are written to during a mission. The MIP bit can also be written to logic 0 by the end user
to stop event logging via the 2-wire bus. By writing a 0 to the MIP bit and stopping the mission, a 0 is
automatically written to the ME bit of the control register. It cannot, however, be written to logic 1 to start
a mission unless the MEM CLR bit is a 1 to signify that the memory has been cleared.
CM - Clear Memory – This bit will trigger the memory to be cleared if the CLR clear enable and COE
clock oscillator enable bits in the control register are set to a 1. This will cause the event log memory,
event count, and start time stamp registers to all be cleared to zeros. Once the memory has been cleared,
the CLR enable bit and the CM bits will be set to zeros and the MEM CLR bit will be set to a 1 to allow a
new mission to begin. Clearing the memory is a two-write process to reduce the risk of accidentally
erasing the memory. The CLR bit must be set to a 1 before the CM bit can be written to a 1. During the
clear memory operation the DS1678 should not be accessed for 500µs while the memory is erased. The
MEM CLR bit should read a 1 before trying to access the cleared memory or registers.
LOBAT - Low Battery Flag – This bit reflects the status of the backup power source connected to the
V
BAT
pin. A logic 1 for this bit indicates an exhausted lithium energy source.
ROF - Roll Over Flag – This bit will be set to a one if the RO bit of the control register is set to a one,
the last data log memory location has been filled and a new event has occurred, which will cause the
time/date stamp to be over written. If RO is set to a 0 (roll over is disabled), the last data log memory
location has been filled and an new event has occurred, ROF will be set to a 1 to indicate that more events
have occurred than the number of available memory locations. The event counter will continue to record
events, even after the event log memory is full. The ROF is cleared by the clear memory command.
ALMF - Alarm Flag – A logic 1 in the alarm flag bit indicates that the current time has matched the
time-of-day alarm registers. If at the same time, the DISx bits are both logic 0’s, the
INT pin will go low
to issue an alarm interrupt. ALMF is a read only bit and is cleared by accessing any of the Alarm register
bytes either with a read or a write. Writing any memory location during a mission will stop the mission. A
mission can not be started when the DISx bits are both set to 0.
EVENT COUNTER
This 3-byte register set provides the number of events that have been logged during the current data
logging operation (also known as a “mission”). The contents of this register can be used by software to
point to the most recent data sample in the event log memory. The data in these registers are cleared when
the event log memory is cleared. The event counter is not incremented when the ETC reaches FFh and
rolls over to the next 16 bits of memory.
ADDRESS POINTER REGISTER
The address pointer register always contains the address that the next data LSB will be written to in the
event log memory. The address pointer registers are located in the main memory map at LSB (3Fh) and