Rainbow Electronics DS1384 - Manual (Page 5)

DS1384
5 of 17
When the address value presented to the DS1384 during the write is in the range of 00000H through
0003FH, one of the 64 on-chip registers will be selected and data will be written into the device.
When the address value presented to the DS1384 during the write is in the range of 00040H through
1FFFFH, an external SRAM location will be selected.
DATA RETENTION MODE
When V
CCI
is within nominal limits (V
CC
> 4.5 volts) the DS1384 can be accessed as described above
with read or write cycles. However, when V
CC
is below the power-fail point, V
PF
, (point at which write
protection occurs) the internal clock registers and external RAM is blocked from access. This is
accomplished internally by inhibiting access to the clock registers via the CE signal. At this time the
power fail output signal ( PFO ) is driven active and will remain active until V
CC
returns to nominal levels.
External RAM access is inhibited in a similar manner by forcing CEO to high level. This level is within
0.2 volts of the V
CCI
input. CEO will remain at this level as long as V
CCI
remains at an out-of-tolerance
condition. When V
CCI
falls below the level of the battery (V
BAT1
or V
BAT2
), power input is switched from
the V
CCI
pin to the V
BAT
pin and the clock registers are maintained from the attached battery supply.
External RAM is also powered by the V
BAT
input when V
CCI
is below V
BAT
pin through the V
CCO
pin. The
V
CCO
pin is capable of supplying 100
µ
A of current to the attached memory with less than 0.3 volts drop
under this condition. On power-up, when V
CCI
returns to in-tolerance conditions, write protection
continues for 150 ms by inhibiting CEO . The PFO signal also remains active during this time. The
DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications
which require added reliability or increased battery capacity. When two batteries are used, the higher of
the two is selected for use. A selected battery will remain as backup supply until it is significantly below
the other. When the selected battery voltage falls below the alternate battery by about 0.6 volts, the
alternate battery is selected and then becomes the backup supply. This switching occurs transparently to
the user and continues until both batteries are exhausted. When only a single battery is required, both
battery inputs can be connected together. However, a more effective method of using a single battery
supply is to ground the unused battery input. When using a single battery, V
BAT1
is the preferred input.
WATCHDOG TIMEKEEPER REGISTERS
The DS1384 Watchdog Timekeeper Controller has 14 internal registers, which are 8 bits wide and
contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar,
Alarm and Watchdog Registers are memory locations, which contain external (user accessible) and
internal copies of the data. The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The
Command Register bits are affected by both internal and external functions. This register will be
discussed later. The 50 bytes of RAM registers are accessed from the external address and data bus and
reside or overlay external static RAM. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day and date
information (see Figure 2). Time of day information is stored in BCD. Registers 3, 5, and 7 contain the
time of day alarm information. Time of day alarm information is stored in BCD. Register B is the
Command Register and information in this register is binary. Register C and D are the Watchdog Alarm
Registers and information, which is stored in these two registers, is in BCD. Registers 0000EH through
register 0003FH are on-chip user bytes and can be used to contain data at the user’s discretion.