Rainbow Electronics DS1251Y - Manual (Page 3)

DS1251/DS1251P
3 of 22
RAM READ MODE
The DS1251 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is
active (low). The unique address specified by the 19 address inputs (A0–A18) defines which of the 512k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within t
ACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable) access
times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t
CO
for CE or
t
OE
for OE , rather than address access.
RAM WRITE MODE
The DS1251 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active)
then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point, V
PF
(point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point, V
SO
(battery supply level), device power is switched from the V
CC
pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when V
CC
is greater than V
PF.
When V
CC
falls below the power-fail point, V
PF
, access to the device is inhibited. If V
PF
is less than V
BAT,
the device power is switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops below V
PF
. If V
PF
is
greater than V
BAT
, the device power is switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops
below V
BAT
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the