Rainbow Electronics DS14287 - Manual (Page 14)

DS14285/DS14287
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that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared
when read and new interrupts which are pending during the read cycle are held until after the cycle is
completed. One, 2, or 3 bits can be set when reading Register C. Each utilized flag bit should be
examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as at
least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is
a one whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is
accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts
have been initiated by the DS14285/DS14287. The act of reading Register C clears all active flag bits and
the IRQF bit.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once
every 122
µ
s. This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same Register A bits which select
the square wave frequency (see Table 2). Changing the Register A bits affects both the square wave
frequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE
bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create
output intervals, or await the next needed software function.
OSCILLATOR CONTROL BITS
When the DS14287 is shipped from the factory, the internal oscillator is turned off. This feature prevents
the lithium energy cell from being used until it is installed in a system. A pattern of 010 in bits 4 through
6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the
oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4
through 6 keep the oscillator off.
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of
Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the
SQW pin. The RS0-RS3 bits in Register A establish the square wave output frequency. These
frequencies are listed in Table 2. The SQW frequency selection shares its 1-of-15 selector with the
periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on
and off under program control with the square wave enable bit (SQWE).