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Bit lasered rom, Figure 3. 64-bit lasered rom, Figure 4. 1-wire crc generator – Rainbow Electronics DS2431 User Manual

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DS2431: 1024-Bit, 1-Wire EEPROM

5 of 23

Figure 2. Hierarchical Structure for 1-Wire Protocol

Available
Commands:

DS2431 Command Level:

Data Field
Affected:

1-Wire ROM Function

Commands (see Figure 9)

DS2431-specific

Memory Function

Commands (see Figure 7)

Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match

64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
64-bit Reg. #, RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag

Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory

64-bit Scratchpad, Flags
64-bit Scratchpad
Data Memory, Register Page
Data Memory, Register Page

64-BIT LASERED ROM

Each DS2431 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X

8

+ X

5

+ X

4

+ 1. Additional information about the Dallas 1-Wire

CRC is available in Application Note 27.

The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the
last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.

Figure 3. 64-Bit Lasered ROM

MSB

LSB

8-Bit

CRC Code

48-Bit Serial Number

8-Bit Family

Code (2Dh)

MSB

LSB

MSB

LSB

MSB LSB

Figure 4. 1-Wire CRC Generator

X

0

X

1

X

2

X

3

X

4

X

5

X

6

X

7

X

8

Polynomial = X

8

+ X

5

+ X

4

+ 1

1

st

STAGE

2

nd

STAGE

3

rd

STAGE

4

th

STAGE

6

th

STAGE

5

th

STAGE

7

th

STAGE

8

th

STAGE

INPUT DATA